This invention relates to clock data recovery circuitry, and more particularly to providing clock data recovery circuitry with a programmable serializer/deserializer with double-edge clocking
An increasingly important type of signaling between devices is signaling in which the clock signal information is embedded in a serial data stream so that no separate clock signal needs to be transmitted. For example, data may be transmitted serially in “packets” of several successive serial data words preceded by a serial “header” that includes several training bits having a predetermined pattern of binary ones and zeros. The clock signal information is embedded in the data signal by the high-to-low and/or low-to-high transitions in that signal, which must have at least one high-to-low or low-to-high transition within a certain number of clock signal cycles. At the receiver the clock signal is “recovered” from the data signal for use in properly processing the data in the data signal. For convenience herein this general type of signaling will be referred to generically as “clock data recovery” or “CDR” signaling.
CDR signaling is now being used in many different signaling protocols. These protocols vary with respect to such parameters as clock signal frequency, header configuration, packet size, data word length, number of parallel channels, etc.
Programmable logic devices (“PLDs”) are well known as shown, for example, by such references as Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. Pat. No. 5,909,126, Jefferson et al. U.S. Pat. No. 6,215,326, and Ngai et al. U.S. patent application Ser. No. 09/516,921, filed Mar. 2, 2000. In general, a PLD is a general-purpose integrated circuit device that is programmable to perform any of a wide range of logic tasks. Rather than having to design and build separate logic circuits for performing different logic tasks, general-purpose PLDs can be programmed in various different ways to perform those various logic tasks. Many manufacturers of electronic circuitry and systems find PLDs to be an advantageous way to provide various components of what they need to produce.
There is a limit to the highest data clock rate that current CDR circuitry can support. High data clock rates can be supported by the use of high clocks and clock signals. However, the use of high clocks and clock signals creates difficulty in routing signals, leads to increasing problems with attendant noise, power, and other issues.
CDR signaling is an area in which it would be highly desirable to have the ability to use PLDs to avoid having to always design and build CDR transmitters and receivers that are specific to each of the many different CDR protocols.
It would also be highly desirable for the CDR circuitry to support higher data clock rates while avoiding the need for high clocks and clock signals.